pipeline stalls造句

例句与造句

1. Otherwise, they would occupy separate entries which increases the chance of pipeline stall.
2. Therefore, the computer can use this instruction to do useful work whether or not its pipeline stalls.
3. By nature, any jump in the code causes a pipeline stall, which is a detriment to performance.
4. One barrier to achieving higher performance through instruction-level parallelism stems from pipeline stalls and flushes due to branches.
5. In contrast, the cipher block chaining ( CBC ) mode of operation incurs significant pipeline stalls that hamper its efficiency and performance.
6. It's difficult to find pipeline stalls in a sentence. 用pipeline stalls造句挺难的
7. Doing so duplicates the condition check ( increasing the size of the code ) but is more efficient because jumps usually cause a pipeline stall.
8. A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls ( an instruction spending more than one clock cycle in a stage ).
9. To avoid unnecessary loading of branch prediction electronics, ( and therefore unnecessary pipeline stalls ) the comparing branch codes should never be used for unconditional jumps.
10. I would have expected the second approach to cause a lot of pipeline stalls because of all the conditional branches, but so far I haven't run benchmarks.
11. However, in superscalar processors there is a penalty for all jumps because they cause pipeline stalls, and programs created for them are more efficient if jumps are removed where possible.
12. The pipeline stalls can be caused by structural hazards ( processor resource limit ), data hazards ( output of one instruction needed by another instruction ) and control hazards ( branching ).
13. If these two assembly pseudocode instructions run in a pipeline, after fetching and decoding the second instruction, the pipeline stalls, waiting until the result of the addition is written and read.
14. This feature can improve the performance of pipelined CPUs by absorbing some of the time wasted if a CPU mispredicts the operation of a conditional branch, and the CPU's pipeline stalls.
15. There are several methods used to deal with hazards, including pipeline stalls / pipeline bubbling, operand forwarding, and in the case of out-of-order execution, the scoreboarding method and the Tomasulo algorithm.
16. Cycle-accurate simulators must ensure that all operations are executed in the proper virtual ( or real if it is possible ) timebranch prediction, cache misses, fetches, pipeline stalls, thread context switching, and many other subtle aspects of microprocessors.
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